<div class="paragraph"> <p>Are you someone that is confused by terms like ARM, AArch64, x86_64, i386, etc when viewing a datasheet or downloads page of a software? These are called CPU architectures and I will help you dip your toes in this topic of computing.</p> </div> <div class="paragraph"> <p>Following is a table that will provide you with a good summary of what each string means:</p> </div> <table class="tableblock frame-all grid-all stretch"> <colgroup> <col style="width: 50%;"> <col style="width: 50%;"> </colgroup> <thead> <tr> <th class="tableblock halign-center valign-middle">CPU Architecture</th> <th class="tableblock halign-center valign-middle">Description</th> </tr> </thead> <tbody> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>x86_64/x86/amd64</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>Same name for 64-bit AMD/Intel CPUs</p> </div></div></td> </tr> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>AArch64/arm64/ARMv8/ARMv9</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>Same name for 64-bit ARM CPUs</p> </div></div></td> </tr> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>i386</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>32-bit AMD/Intel CPUs</p> </div></div></td> </tr> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>AArch32/arm/ARMv1 to ARMv7</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>Same name for 32-bit ARM CPUs</p> </div></div></td> </tr> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>rv64gc/rv64g</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>Same name for 64-bit RISC-V CPUs</p> </div></div></td> </tr> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>ppc64le 64-bit</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>PowerPC CPUs with little-endian memory ordering</p> </div></div></td> </tr> </tbody> </table> <div class="paragraph"> <p>Reading from left to right is the preference of using that term to describe the CPU architecture over the other, alternatively used terms on its right.</p> </div> <div class="paragraph"> <p>If you are nerdy like me and want a more in-depth explanation, do read on!</p> </div> <div class="sect1"> <h2 id="_general_overview_cpu_architectures">General overview: CPU architectures</h2> <div class="sectionbody"> <div class="paragraph"> <p>The terms that I listed above, generally speaking, are CPU architectures. Though, pedantically speaking, these are what a computer engineer calls a CPU ISA (Instruction Set Architecture).</p> </div> <div class="paragraph"> <p>A CPU ISA is what defines how the 1’s and 0’s of binary are interpreted by your CPU.</p> </div> <div class="paragraph"> <p>There are a few supersets of these CPU ISAs.</p> </div> <div class="ulist"> <ul> <li> <p>x86 (AMD/Intel)</p> </li> <li> <p>ARM</p> </li> <li> <p>RISC-V</p> </li> <li> <p>PowerPC (still alive at IBM)</p> </li> </ul> </div> <div class="paragraph"> <p>There are more CPU ISAs like MIPS, SPARC, DEC Alpha, etc. But the ones I listed above are the ones that are still widely used today (in some capacity).</p> </div> <div class="paragraph"> <p>The above listed ISAs have at least two subsets. This is mainly based on the width of the memory bus. The width of the memory bus denotes how many bits can be transferred between the CPU and the RAM in one go. There are several widths for the memory bus, but the two most important widths are 32-bit wide memory bus and a 64-bit wide memory bus.</p> </div> <div class="exampleblock"> <div class="content"> <div class="paragraph"> <p>The 32-bit counterparts of the CPU ISAs are either a relic of the past, kept alive for legacy support or are only used in micro-controllers. It is safe to assume that any new hardware is 64-bit (especially consumer facing hardware).</p> </div> </div> </div> </div> </div> <div class="sect1"> <h2 id="_x86_amdintel">x86 (AMD/Intel)</h2> <div class="sectionbody"> <div class="paragraph"> <p>The x86 CPU ISA comes primarily from Intel as Intel was the one who created it in the first place with the 8085 micro-processor. The 8085 micro-processor had a 16-bit wide memory bus. Later, AMD came to the game and followed Intel’s footsteps until AMD created their own superset 64-bit architecture, surpassing Intel.</p> </div> <div class="paragraph"> <p>The subsets of x86 architecture are as follows:</p> </div> <div class="ulist"> <ul> <li> <p><strong>i386</strong>: If you own a CPU from pre-2007, this is likely your CPU architecture. It is the 32-bit "variant" of the currently known x86 architecture from AMD/Intel.</p> </li> <li> <p><strong>x86_64/x86/amd64</strong>: All three terms are used interchangibly depending on the project you look at. But they all refer to the 64-bit "variant" of the x86 AMD/Intel architecture. Regardless, the string x86_64 is widely used (and preferred) over x86 and amd64. An example of this is that the FreeBSD project refers to the 64-bit x86 architecture as amd64 while Linux and macOS refer to this as x86_64.</p> </li> </ul> </div> <div class="exampleblock"> <div class="content"> <div class="paragraph"> <p>Since AMD beat Intel at creating a 64-bit ISA, some projects like FreeBSD refer to the 64-bit variant of x86 as amd64. But the more widely accepted term is still x86_64.</p> </div> </div> </div> <div class="paragraph"> <p>The x86 string for CPU ISA is a special one. You see, during the transition from 32-bit x86 (i386) to 64-bit x86 (x86_64), the CPU vendors made sure that the CPU can run both, 32-bit and 64-bit instructions. Therefore, sometimes when you read x86, it can also mean "It will run only on a 64-bit computer, but if that computer can run 32-bit instructions, you can run 32-bit user software on it."</p> </div> <div class="paragraph"> <p>This ambuiguity of x86—meaning 64-bit processors that can also run 32-bit code—is mainly for/due-to Operating Systems that run on 64-bit processors, but allow the user of said OS to run 32-bit software. Windows makes use of this with a feature called "compatibility mode".</p> </div> <div class="paragraph"> <p>Let’s recap, there are two CPU architectures for the CPUs designed by AMD and Intel. They are 32-bit (i386) and 64-bit (x86_84).</p> </div> </div> </div> <div class="sect1"> <h2 id="_extra_intel">Extra intel</h2> <div class="sectionbody"> <div class="quoteblock"> <blockquote> <div class="paragraph"> <p>(Yeah! I am funny)</p> </div> </blockquote> </div> <div class="paragraph"> <p>The x86_64 ISA also has sub-sets. All of these subsets are 64-bit but have various features added. Especially SIMD (Single Instruction Multiple Data) instructions.</p> </div> <div class="ulist"> <ul> <li> <p><strong>x86_64-v1</strong>: The base x86_64 ISA that almost everyone is familar with. When someone says x86_64, they are most likely referring to the x86_64-v1 ISA.</p> </li> <li> <p><strong>x86_64-v2</strong>: This adds more instructions like SSE3 (Streaming SIMD Extensions 3) as extensions.</p> </li> <li> <p><strong>x86_64-v3</strong>: Adds instructions like AVX (Advance Vector eXtensions) and AVX2 which can use up-to 256-bit wide CPU registers! This can massively parallelize your computations if you can take advantage.</p> </li> <li> <p><strong>x86_64-v4</strong>: Iterates upon the x86_64-v3 ISA by adding more SIMD instruction as extensions. Such as AVX256 and AVX512. The later can use up-to 512-bit wide CPU registers!</p> </li> </ul> </div> </div> </div> <div class="sect1"> <h2 id="_arm">ARM</h2> <div class="sectionbody"> <div class="paragraph"> <p>ARM is a company that creates its own specification for a CPU ISA, designs and licenses their own CPU cores and also allows other companies to design their own CPU cores using the ARM CPU ISA. (The last part felt like an SQL query!)</p> </div> <div class="paragraph"> <p>You might have heard about ARM because of SBCs (Single Board Computer) like the Raspberry Pi line up of SBCs. But their CPUs are also widely used in mobile phones. Recently, Apple has switched from x86_64 processors to using their own design of ARM processors in their laptop and desktop offerings.</p> </div> <div class="paragraph"> <p>Like any CPU architecture, there are two subsets based on the width of the memory bus.</p> </div> <div class="paragraph"> <p>The officially recognised names for the 32-bit and 64-bit ARM architectures are AArch32 and AArch64 respectively. The 'AArch' string stands for 'Arm Architecture'. These are modes a CPU can be in, for executing instructions.</p> </div> <div class="paragraph"> <p>The actual specification of an instruction that complies with ARM’s CPU ISA are named ARMvX where X refers to a generation number of a specification. To this date, there have been 9 major versions of this specification. Ranging from ARMv1 to ARMv7, which is defines a CPU architecture specification for 32-bit CPUs. While ARMv8 and ARMv9 are specifications for the 64-bit ARM CPUs. (More info here.)</p> </div> <div class="exampleblock"> <div class="content"> <div class="paragraph"> <p>Each ARM CPU specification has further sub-specifications. Taking ARMv8 as an example, we have ARMv8-R, ARMv8-A, ARMv8.1-A, ARMv8.2-A, ARMv8.3-A, ARMv8.4-A, ARMv8.5-A, ARMv8.6-A, ARMv8.7-A, ARMv8.8-A and ARMv8.9-A. The -A stands for "Applications cores" and -R stands for "Real-time cores".</p> </div> </div> </div> <div class="paragraph"> <p>You might be wondering why some people call it arm64 even when AArch64 is the officially recognized name for 64-bit ARM architecture. The reason is two-folds:</p> </div> <div class="olist arabic"> <ol class="arabic"> <li> <p>The name arm64 caught on before AArch64 was decided upon by ARM. (ARM also refers to the 64-bit ARM architecture as arm64 in some of it’s official documentation… 😬)</p> </li> <li> <p>Linus Torvalds dislikes the AArch64 name. Therefore the Linux codebase largely refers to AArch64 as arm64. But it will still report aarch64 when you do a uname -m.</p> </li> </ol> </div> <div class="paragraph"> <p>Therefore, for 32-bit ARM CPUs, you should look for the string AArch32 but sometimes it might also be arm or armv7. Similarly, for 64-bit ARM CPUs, you should look for the string AArch64 but sometimes it might also be arm64 or ARMv8 or ARMv9.</p> </div> </div> </div> <div class="sect1"> <h2 id="_risc_v">RISC-V</h2> <div class="sectionbody"> <div class="paragraph"> <p>RISC-V is an open source specification of a CPU ISA. This doesn’t mean that the CPUs themselves are open source! It is a standard, kind of like Ethernet. The Ethernet specification is open source but the cables, routers and switches you purchase do cost money. Same deal with RISC-V CPUs. :)</p> </div> <div class="paragraph"> <p>Though, this has not prevented people from creating RISC-V cores that are freely available (as designs; not as physical cores/SoC) under an open source license. Here is link: <a href="https://github.com/openhwgroup?ref=itsfoss.com">one such effort</a>.</p> </div> <div class="exampleblock"> <div class="content"> <div class="paragraph"> <p><strong>TL;DR</strong>: You sould be looking for the string rv64gc if you are looking for software to run on RISC-V consumer CPUs. This is what a large number of Linux distributions have agreed upon.</p> </div> </div> </div> <div class="paragraph"> <p>Just like any CPU architecture, RISC-V has 32-bit and 64-bit CPU architectures. Since RISC-V is very new (in the terms of a CPU ISA), all major CPU cores in consumer/client side are usually 64-bit CPUs. The 32-bit designs are mostly micro-controllers that have a very specific use-case.</p> </div> <div class="paragraph"> <p>What they do differ in, are CPU extensions. The absolute minimum extension one needs to implement to be called a RISC-V CPU is the 'Base Integer Instruction Set' (rv64i).</p> </div> <div class="paragraph"> <p>A table of a few extensions and the description is as below:</p> </div> <table class="tableblock frame-all grid-all stretch"> <colgroup> <col style="width: 50%;"> <col style="width: 50%;"> </colgroup> <thead> <tr> <th class="tableblock halign-center valign-middle">Extension name</th> <th class="tableblock halign-center valign-middle">Description</th> </tr> </thead> <tbody> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>rv64i</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>64-bit Base Integer Instruction Set (mandatory)</p> </div></div></td> </tr> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>m</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>Multiplication and Division instructions</p> </div></div></td> </tr> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>a</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>Atomic instructions</p> </div></div></td> </tr> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>f</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>Single-precision floating point instructions</p> </div></div></td> </tr> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>d</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>Double-precision floating point instructions</p> </div></div></td> </tr> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>g</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>Alias; A collection of extensions necessary to run a general-purpose OS (includes imafd)</p> </div></div></td> </tr> <tr> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>c</p> </div></div></td> <td class="tableblock halign-center valign-middle"><div class="content"><div class="paragraph"> <p>Compressed instructions</p> </div></div></td> </tr> </tbody> </table> <div class="exampleblock"> <div class="content"> <div class="paragraph"> <p>There are other extensions like Zicsr and Zifencei that sit between the d and g extensions but I deliberately didn’t include them as to not scare you off.</p> </div> <div class="paragraph"> <p>So technically, (as of writing this article) rv64g is actually rv64imafdZicsrZifencei. <strong>evil laughter</strong></p> </div> </div> </div> </div> </div> <div class="sect1"> <h2 id="_powerpc">PowerPC</h2> <div class="sectionbody"> <div class="paragraph"> <p>PowerPC was very popular CPU architecture in the early days of Apple, IBM and Motorola partnership. It was the CPU architecture that Apple used in their entire consumer line-up until they switched from PowerPC to Intel’s x86.</p> </div> <div class="paragraph"> <p>PowerPC initially had big-endian memory ordering. Later, when a 64-bit architecture was introduced, an option to use little-endianness was added. This was done to be compatible with Intel’s memory ordering (to prevent software bugs) which has always been little-endian. I could go on and on about endianness but you are better served with this Mozilla document to learn more about endianness.</p> </div> <div class="paragraph"> <p>Since endianness is also a factor here, there are 3 architectures of PowerPC:</p> </div> <div class="ulist"> <ul> <li> <p><strong>powerpc</strong>: The 32-bit PowerPC architecture.</p> </li> <li> <p><strong>ppc64</strong>: The 64-bit PowerPC architecture with big-endian memory ordering.</p> </li> <li> <p><strong>ppc64le</strong>: The 64-bit PowerPC architecture with little-endian memory ordering. As of now, ppc64le is widely used.</p> </li> </ul> </div> </div> </div> <div class="sect1"> <h2 id="_conclusion">Conclusion</h2> <div class="sectionbody"> <div class="paragraph"> <p>There are many CPU architectures out there in the wild. For each CPU architecture, there are 32-bit and 64-bit subsets. There are CPUs that offer x86, ARM, RISC-V and PowerPC architectures.</p> </div> <div class="paragraph"> <p>The x86 is the most widely and easily available CPU architecture, since that is what Intel and AMD use. There are also offerings from ARM which are almost exclusively used in mobile phones and accessible SBCs.</p> </div> <div class="paragraph"> <p>RISC-V is in an ongoing effort to make the hardware more widely accessible. I have an SBC that has a RISC-V CPU ;)</p> </div> <div class="paragraph"> <p>PowerPC is mainly found in servers, at least at the moment.</p> </div> </div> </div>